Compensator

His) 4s)

1m = 4V

Fig, 9.23 System small-signal яс model, design example.

Tis)

v.. 2

f9.45)

Tlie quiescent value ofthe control vtdtage, V, must satisfy Eq. (7.173). Hence,

V, = DV =2.14 V

(9.46)

Thtis, the quiescent conditions ofthe system are known. It remains to design the compensatorgain G{s).

A small-signal ac model ofthe regulator system is illustrated in Fig. 9.23. The buck converter ac model is represented in canonical form. Disturhances in the input voltage and in the load current are modeled. For generality, reference voltage variations are included in the diagram; in a dc voltage regulator, these variations are normally zero.

The t)pen-loop converter transfer functions are discussed in the previous chapters. The open-loop control-to-output transfer function is

(9.47)

The ореп-кюр control-to-output transfer function contains two poles, and can be written in the foltowing normalized form;

60 dBV

10 Ki 100 Hi IkUz

Fig. 9.24 Converter small-signal comrol-to-output transfer function (7, (jesign exannple,

10 kHz lOOkHz

C.,(s) = G, --l +

By equating like coefficients in Eqs. (9.47) antl (9.48), one finds that the dc gain, corner frequency, and Q-factor are given by

t;=0 = 28V

e.= R\/Y = 9.5 19.5 dB

(9.49)

In practice, parasitic loss elentents, such as the capacitor equivalent series resistance (esr). would cause a lower Q-factor tt) he observed. Figure 9.24 contains a Bode diagram of G.Js). The open-l(Xip line-to-output transfer function is

(9.50)

This transfer function contains the same poles as in Gs), and can be written in the normalized form

(9.S1)

with G o = D. The open-loop output impedance of the buck converter is

l+s+.iLC

(9.52)

Load current variation

ac line varialion

vanalion

Convener power stage

fig. 9.2s System bioclc diagram, design example.

Use of the.se e(]uatioiis to reptesent the converter in block-diagratri form leads to the complete systetn block diagram of Fig. 9.25. The loop gain of the system is

Substitution ofEq. (9.48) into (9.53) leads to

aSs)H(s) V

(9.53)

(5.54)

10 Нг

100 Hi

1кНг

10 Ш£

Fig. 9.26 Uncompensated loop gain design exatnple.