The transistor current waveform toiticides with the input current waveform j.W. which is sltetched in Fig. 6J2. The rms value of this waveform is

So the total active switch stress is

The load power fjf can be expressed in terms of Iand / by solution of the equivalent circuit model, Fig. й.ЗЗ(Ь). The resuh is

Use of Eq, (6.44) toelimiitate from Eq. (6.55), and evaluatioit of Eq. (6.52), leads to

The transistor titilizatioit Lteitds to zero at D ~ 0 and at D = 1, and reaches a maximum of (У ~ 0.385 at D= 1/3.

For given values of K V, aitd the load power, the designer can arbitrarily choose the duty cycle D. The turns ratio is then chosen to satisfy Eq. (6.44), as follows:

>~--%

At low duty cycle, the transistor rms current becomes large because the transformer turns ratio must be large. At a duty cycle approaching one, the transistor peak voltage is large. So the choice D = 1/3 is a good one, which minimizes the product of peak transistor voltage and rms transistor ctirrent. In practice, the converter must be optimized to meet a number of different criteria, so a somewhat different duty cycle may be chosen. Also, the converter must usually be designed to operate with some given range of load powers and input voltages: this can lead to a different choice of D, as well as to reduced switch utilization.

For a simple comparison between converters, the switch utilizations of a number of i.solated and nonisolated converters are collected in Table 6.1. For simplicity, the formulas assume that the convetter is designed to function at a single operating point, that is, with no variations in V V, or

It can be .seen that the nonisolated buck and boost converters operate most efficiently when their conversion ratios МФ) are near one. In the case of the boost converter, the switch utilization is greater than one for D < 0.382, and approaches infinity as D tends to zero. The reason for this is that, at D = 0, the transistor is always off and heitce its rms current is zero. But at D = 0, V= V, so the output power is nonzero. All of the load power flows through the diode rather than the transistor. Of course, if it is desired that V= V, then it would be best to eliminate the boost converter, and directly connect the load to the input voltage. But it is nonetheless true that if the output voltage Vis not too much greater than V, then a large amount of power can be controlled by a relatively small transistor. Similar arguments apply to the buck converter: all of the load power must flow through the transistor and hence U < 1, yet converter efficiency and cost per watt are optimized when the output voltage Vis not too much smaller than the input voltage.

6.4 Convener Evaluation and Design

Tabic d.i Active switch utilizations of some cominon dc-dc converters, single operating point

Incorporation of an isolation transformer leads to reduced switch utilization. In general, transformer-isolated buck-derived converters should be designed to operate at as large a duty cycle as other considerations will allow. Even so, the switch utilization is redticed to [/<0,353, meaning that the switch stress is increased by a factor of approximately 2.S as compared with the nonisolated buck converter at D = 1. On the other hand, the transformer turns ratio can be chosen to match the load voltage to the input voltage and better optimize the converter. Forexample, in a full-bridge buck-derived converter operating with Vj, = 500 V and V= 5 V, the turns ratio could be chosen to be nearly 1(Ю:1, leading to a duty cycle close to one and switch utilization of approximately 0.35. To obtain a 1 kW output power, the total transistor stress would be 1 kW/0.35 - 2.86 kVA. By comparison, the nonisolated buck converter would operate with aduty cycle ofO.Oi and a switch utilization of0.1. Its total switch stress would be 1 kW/0,1 = 10 kVA; transistors with larger rated currents and lower on-resistances would be needed. Similar arguments apply to the transformer-isolated boost-derived converters: these converters are better optimized when they operate at low duty cycles.

The nonisolated btick-boost, nonisolated SEPIC, nonisolated Cuk converter, and the isolated SEPIC, flyback, and Cuk converters have similar switch utilizations. In all of these converters, [/<0.385, which is approximately the same as in the isolated buck-derived converters. So the nonisolated versions of these converters tend to have k)wer switch titilizations than the buck or boost converters; however, isolation can be obtained with no additional penalty in switch stress. Switch utilization of a single-operating-point design is maximized when the turns ratio is chosen such thatD = 1/3.

The cost of the active semiconductor devices of a converter approach can be estimated using the converter switch utilization, as follows:

semicoiiri tic tor cost per kW output power

semiconductor device cost per rated kVA

(6.59)

The semiconductor device cost per rated kVA is equal to the cost of u semiconductor device, divided by

the products of its maximum voltage rating and its maximum rms current capability, expressed in $/kVA. This figure depends on a variety of factors, including the device type, packaging, voltage and power levels, and market volume. A typical U.S. value in ЭХХ) is less than $1 /kVA. Voltage and ctirrent derating is required to obtain reliable operation of the seiniconductor devices. A typical dcsigti guideline is that the worst-case peak transistor voltage (including transients, voltage spikes due to ringing, and all other anticipated events) should not exceed 75% of the rated transistor voltage, leading to a voltage derating factor of (0.75). Hence, the cost of the active semiconductor switches in a 20СЮ isolated dc~dc converter is typically in the range $1 to SIO per kW of output power for medium to high-power applications.

6.4.2 Design Using Cumputer Spreadsheet

Computer spreadsheets are a useful tool for performing converter Urade studies and designs. Given specifications regarding the desired output voltage V, the ranges of the input voltage and the load power laaii desired output voltage ripple Av, the switching frequency f, etc., various ilesign options can be explored. The transfortner turns ratio and the indtictor current ripple Д/ can be taken as design variables chosen by the engineer. The range of duty cycle variations and the inductor and capacitor component val ues can then be comptited. Worst-case values of the currents and voltages applied to the various power stage elements can also be evaluated, as well as the sizes of the magnetic elements. By investigating sev era! choices of the design variables, a gtKid compromise between the worst-case voltage stresses and cur rent stresses can be found.

A short spreadsheet example is given in Table 6.2. The convetter operates from a dc voltage derived by rectifying a 230 V ± 20% ac source voltage. The converter dc input voltage is therefore 230 Л V ±20%, The load voltage is a regulated 15 V dc, with switching ripple Av no greater than 0.1 V. The load power can vary over the range 20 W to 200 W. It is desired to operate with a switching frequency of = lt)() kHz. These values are entered as specifications, at the top of the spreadsheet. The design of a forward converter. Fig. 6.22, and of a flyback converter. Fig. 6.30(d), to meet these specifications is investigated in the spreadsheet Continuous conduction mode designs are investigated: the inductor ctirrent ripple Дг is chosen small enough that the converter operates in CCM at full load power. Depending on the choice of Д/, the converter may operate in either CCM or DCM at minimum load power.

For the single-transistor forward converter, the turns ratios /(j/n, and Wi/i as well as the inductor current ripple Ai, can be taken as design variables. For this example, the reset-winding turns ratio П21П[ is chosen to be one, and hence the duty cycle is limited toD<0.5 as given by Eq. (6,35), The maximum duty cycle is computed first. The outptit voltage of the forward converter, in continuous conduction mode, is given by Eq. (6.36), Solution for the duty cycle D leads to

The maximum value of D occurs at minimum and at full load, and is given in Table 6.2. The minimum CCM value of D, occurrmg at maximum V, is also listed.

The value of the inductance L is comptited next. The magnittide of the inductor current ripple Д can be c[>mputed in a manner similar to that used for the nonisolated btick converter to obtain Eq. (2.15). The result is

A, = - (6,6i)